1. Field of the Invention
This invention relates to the fabrication and testing of monolithic integrated circuit wafers. More particularly, this invention relates to the addition to state-of-the-art wafers of a new conductive test circuit integrated on the wafer during manufacture which may be used to test the networks between the dice on the wafer so they may be tested to prove that the wafer meets quality standards. In addition, the method of testing this new wafer is disclosed.
2. Description of the Prior Art
While no satisfactory method has heretofore been developed which meets the need for testing networks on wafers, there have been developed ways of testing the integrated circuit dice themselves, as may be seen from U.S. Pat. No. 4,183,460 granted Jan. 15, 1980, and the reference shown therein, which disclosure is incorporated herein by reference. This patent is deemed illustrative of the state of the art. It is also well known to use testing networks on printed circuit boards on which each die, after testing and packaging, is inserted.
Current state-of-the-art tests on monolithic integrated circuit wafers are performed by automatic testers which sequence across the wafer, die to die, to identify each workable die, before the wafer is scribed. If the dice is defective, a mark is made over each defective die, and it is discarded. Such commercially available machines include those manufactured by various corporations which manufacture the chips, or they can be obtained commercially as fully automatic wafer probe systems from Pacific Western Systems, Inc., 505 E. Evelyn, Mt. View, CA 94041 or Electro-Glas, Inc., 2901 Coronado Dr., Santa Clara, CA 95051. In addition, probe equipment can be obtained from Kulicke Soffa Industry, Inc., 507 Prudential Rd., Horsham, PA 19044, which probe equipment interfaces with commercially available I. C. Test Equipment such as made by Fairchild, Teradyne, etc.
In addition, printed circuit board testers exist which insert pin probes at a plurality of points on the printed circuit boards, which pins are sequenced to determine whether the networks, now defined by the packaged circuits placed in the board and soldered or otherwise bonded in place, have a proper connection. In this art, it is known to place small fixed resistors in a circuit so that tests being made can measure whether the circuit has a known resistance.
However, it has become possible to build full scale wafers now because the yield of good dice on the wafer has increased. A number of theoretical advantages arise from what may be called wafer scale integration. In order to achieve faster switching speeds, or conversely, smaller signal propagation times, it has been recognized that the die which contains the integrated circuits could be connected on the wafer itself. This requires a network being formed on the wafer by masking or by electron beam pattern generation. This can make use of the space between dice, or the whole wafer as a network. In this latter instance, the individual die from another wafer is directly bonded to the network of the wafer containing the network. In the former case, the ultimate wafer scale integration is achieved, for the entire wafer can be utilized for its best tested function.
The problem with machines constructed on wafer scale is effective testing of the circuits so constructed. It is to this problem that the invention which I have described below is directed.